module ClkSwitch(
    inclk1,
    inclk2,
    rst_n,
    sel,

    outclk,
);


reg     pos_reg0;
reg     pos_reg1;
reg     neg_reg0;
reg     neg_reg1;

always @(posedge clk1 or negedge rst_n)begin
    if(!rst_n) pos_reg0 <= 1'b0;
    else       pos_reg0 <= ~neg_reg1 & sel;
end

always @(negedge clk1 or negedge rst_n)begin
    if(!rst_n) pos_reg1 <= 1'b0;
    else       pos_reg1 <= pos_reg0;
end

always @(posedge clk0 or negedge rst_n)begin
    if(!rst_n) neg_reg0 <= 1'b0;
    else       neg_reg0 <= ~sel & ~pos_reg1;
end

always @(negedge clk0 or negedge rst_n)begin
    if(!rst_n) neg_reg1 <= 1'b0;
    else       neg_reg1 <= neg_reg0;
end

assign outclk = (neg_reg1 & inclk1) | (pos_reg1 & inclk0);

endmodule